keysight m3100a pxie digitizers with optional real-time sequencing and fpga programming 100 msa/s, 14 bits, 4/8 channels data sheet
02 | keysight | m3100a pxie digitizer with optional real-time sequencing and fpga programming - data sheet improve your measurement fidelity, signal integrity and measurement throughput the m3102a are high-performance, high-bandwidth digitizers with an advanced data acquisition system (daq). performance meets simplicity thanks to easy-to- use programming libraries, real-time sequencing technology (hvi hard virtual instrumentation), and graphical fpga programming technology. features 100 msa/s simultaneous sampling, 14 bits, 4/8 channels, 100 mhz bw 1 advanced data acquisition system (daq) C flexible triggering (hw trigger, hvi trigger, sw trigger) C programmable cycles and data bursts to avoid pc saturation optional hw programming for high-performance applications C real-time sequencing (hvi technology) C fpga programming C xilinx kintex-7, 325t or 410t fpga up to 2 gb of onboard ram (~ 1 gsamples) mechanical/interface C 1 slot 3u (pxie) C up to 1.6 gb/s transfer bw with p2p capabilities (pcie gen 2) C independent dma channels for fast and efficient data transfer applications general purpose digitizer hardware-in-the-loop (hil)/automated test equipment (ate) r&d/scientific research equipment aerospace & defense (a/d) 1. 100 mhz refer to the front end bandwidth. this digitizer can operate in 1st and 2nd nyquist zones (using undersampling technique), but its real-time bw is limited by nyquist to some 50 mhz. as an example for a band-limited signal of 70 mhz with a 10 mhz signal bandwidth the aliased component will appear between 25 to 35 mhz (30 5 mhz).
03 | keysight | m3100a pxie digitizer with optional real-time sequencing and fpga programming - data sheet programming technology and software tools software programming C easy-to-use native programming libraries for most common languages: c, c++, visual studio, labview, matlab, python, and more hardware programming (optional) C real-time sequencing (hard virtual instrumentation or hvi technology) C graphical flowchart-style m3601a design environment (-hv1 option required on hw) C ultra-fast, fully-parallelized hard real-time execution C ultra-fast, time-deterministic decision-making C off-the-shelf inter-module synchronization & data exchange C fpga programming C graphical m3602a fpga design environment (-fp1 option required on hw) C no fpga know-how required C include high-level to low-level design elements: off-the-shelf dsp blocks, matlab/ simulink designs, xilinx core generator ip cores, xilinx vivado/ise projects, vhdl or verilog code C ultra-fast, one-click compiling and on-the-fly programming no programming C ready-to-use sd1 spf (software front panels) pxie arbitrary waveform generators, digitizers and combination modules product type outputs (awgs) inputs (digitizers) speed (msa/s) bits ch bw (mhz) speed (msa/s) bits ch bw (mhz) m3202a awg 1000 14 2/4 dc-400 m3201a awg 500 16 2/4 dc-200 m3102a digitizer 500 14 2/4 dc-200 m3100a digitizer 100 14 4/8 dc-10 0 m3302a combo 500 16 2 dc-200 500 14 2 dc-200 M3300A combo 500 16 2/4 dc-200 100 14 4/8 dc-10 0
04 | keysight | m3100a pxie digitizer with optional real-time sequencing and fpga programming - data sheet functional block diagram figure 1. m3100a input functional block diagram, all channels have identical input structure ordering information 1 product description m3100a pxie digitizer: 100 msa/s, 14 bits options description m3100a-ch4 / -ch8 four channels 2 / eight channels m3100a-clf fixed sampling clock, low jitter 2 m3100a-m01 / -m12 / -m20 memory 16 mb, 8 msamples 2 / 128 mb, 60 msamples / 2 gb, 1 gsamples hw programming options description m3100a-hvi enabled hvi programming, requires an hvi design environment license (m3601a) m3100a-fp1 enabled fpga programming, requires -k32 or -k41 option and an fpga design environment license (m3602a) m3100a-k32 / -k41 fpga, xilinx 7k325t / 7k410t, required for -fp1 option only (needs memory option -m20) related software description m3601a hvi design environment m3602a fpga design environment 1. all options must be selected at time of purchase and are not upgradable 2. these options represent the standard configuration channel 1 channel x channel 1 output data acquisition (daqx) full scale, z, coupling (as available) prescaler analog trigger channel x output channel n input settings channel n output
05 | keysight | m3100a pxie digitizer with optional real-time sequencing and fpga programming - data sheet technical specifications and characteristics general characteristics m3100a-ch4 m3100a-ch8 parameter min typ max min typ max units comments inputs and outputs channels 4 8 out reference clock 1 1 1 out reference clock 2 1 1 in triggers/markers 1, 3 1 1 in/out reconfigurable triggers/markers 2, 3 8 8 in/out reconfigurable input channels overview sampling rate 100 100 msa/s voltage resolution 14 14 bits input frequency dc 100 dc 100 mhz real-time bw 50 50 mhz time skew <50 <50 ps between channels built-in functionalities input conditioning blocks 4 8 1 per channel analog trigger processors 4 8 1 per channel data acquisition blocks 4 8 1 per channel onboard memory ram memory 16 2048 16 2048 mbytes 1. at front panel 2. at backplane 3. markers available from firmware version v3.0 or later
06 | keysight | m3100a pxie digitizer with optional real-time sequencing and fpga programming - data sheet i/o specifications analog input characteristics number of channels ch4 or ch8 sampling rate 100 msa/s option clf configurable inputs: impedance 50 or 1 m (hiz) configurable inputs: coupling ac or dc input voltage range (50) 400 mvpp to 6vpp (continue: variable attenuator at input) input voltage range (hiz) 200 mvpp to 20vpp (continue: variable attenuator at input) bandwidth limit filters 100 mhz effective number of bits (enob) 1 10.8 bits @30mhz (typical) noise floor ?142 dbm/hz @30 mhz (typical) sinad 67 db @30 mhz (typical) spurious free dynamic range (sfdr) + total harmonic distorsion 79 dbc (typical) 1. measured at -1 dbfs input signal with 1.5 vpp 50 m3100a parameter min typ max units comments reference clock output frequency 10 or 100 mhz generated from the internal clock. user selectable voltage 800 mvpp on a 50 load power 2 dbm on a 50 load source impedance 50 ac coupled external i/o trigger/marker v ih 2 5 v v il 0 0.8 v v oh 2.4 3.3 v on a high z load v ol 0 0.5 v on a high z load input impedance 10 k source impedance ttl C speed 500 mbps
07 | keysight | m3100a pxie digitizer with optional real-time sequencing and fpga programming - data sheet data acquisition blocks (daqs) specifications m3100a-ch4 m3100a-ch8 parameter min typ max min typ max units comments general specifications daqs 4 8 1 per channel aggregated speed 400 800 msa/s for all onboard daqs combined acquisition burst multiple 5 5 samples burst length must be a multiple of this value acquisition ram capacity 15 957m 15 957m samples maximum depends on onboard ram acquisition ram capacity effic. 93.5 93.5 % effic. = waveform size / waveform size in ram trigger selec. selec. hardware trigger (analog channels, input trigger, backplane triggers), software trigger daq specifications speed 100 100 msa/s per daq resolution 14 14 bits clock system specifications m3100a-ch4 m3100a-ch8 parameter min typ max min typ max units comments general specifications clock frequency 100 100 mhz
08 | keysight | m3100a pxie digitizer with optional real-time sequencing and fpga programming - data sheet system specifications environmental specifications (pxi express) m3100a-ch4 m3100a-ch8 parameter min typ max min typ max units comments system bus slots 1 1 slot pxi express (compactpci express compatible) pci express type gen 1 gen 2 gen 1 gen 2 C automatic gen negotiation, chassis dependent pci express link 1 4 1 4 lanes automatic lane negotiation, chassis dependent pci express speed 400 1600 400 1600 mbytes/s depends on # of lanes, chassis, congestion, and more sustainable throughput 200 800 200 800 mpoints/s depends on # of lanes, chassis, congestion, and more power dissipation 3.3v pxie power supply 1.5 1.5 a ~ 5 w 12v pxie power supply 2 2 a ~ 24 w environmental 1 temperature range operating non-operating 0 to +55c (10,000 feet) -40 to +70 c (up to 15,000 feet) max operative altitude 2000 m (10,000 feet) operating humidity range (%rh) 10 to 95% at 40 c non-operating humidity range (%rh): 5 to 95 5 to 95% calibration interval 1 year emc complies with european emc directive C iec/en 61326-1 C cispr pub 11 group 1, class a this ism device is in compliance with canadian ices-001 cet appareil ism est conforme la norme nmb-001 du canada. this ism device is in compliance with australian and new zealand rcm this ism device is in compliance with south korea emc kcc 1. samples of this product have been type tested in accordance with the keysight environmental test manual and verified to be robust against the environ - mental stresses of storage, transportation and end-use; those stresses include but are not limited to temperature, humidity, shock, vibration, altitude and power line conditions. test methods are aligned with iec 60068-2 and levels are similar to mil-prf-28800f class 3.
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